Market demand for smaller, lighter, and more powerful electronic devices drives the development of more compact semiconductor devices and increased functionality. Demand for electronic devices, such as cellular telephones, personal digital assistants, and portable computing devices, contributes heavily to the overall market demand. Development of more compact semiconductor devices and increased functionality has led to thinner semiconductor chips and packaging technologies, such as wafer level packaging (WLP).
WLP refers to the technology of packaging semiconductor chips at the wafer level, instead of the traditional process of packaging semiconductor chips one at a time. WLP is a chip-scale packaging technology, since the resulting package is substantially the same size as the chip. Packaging via wafer level fabrication processes reduces packaging time and inventory, which reduces costs.
Development of more compact semiconductor devices and increased functionality has led to thinner vertical power transistors. Typically, vertical power transistors have two contacts on one face and one contact on an opposing face. In the on state, current flows from one face to the other face. A vertical power MOSFET, usually, has source and gate contacts on one face and a drain contact on the other face. The vertical power MOSFET exhibits an on resistance between the drain and source terminals, where the resistance of the epitaxial layer is a primary factor in the on resistance of the transistor. Manufacturing a thinner vertical power MOSFET is one way of decreasing the on resistance of the transistor.
For these and other reasons, there is a need for the present invention.